Due to hot carrier effects, which are pronounced in sub-micron geometries, there is a tradeoff between performance and reliability when selecting an appropriate channel length for field-effect transistors, such as MOSFETs or IGFETs. A shorter channel length creates a correspondingly greater electric field between the source and the drain of the transistor, which increases drive current (I.sub.D) On one hand, an increased drive current due to a shorter channel length is able to more rapidly charge or discharge the load capacitance of the transistor. Consequently, a circuit including the transistor can run at higher frequencies. On the other hand, an increased electric field, particularly near the drain region, causes an increase in "hot carrier" effects, in which accelerated electrons ionize the silicon lattice, generating pairs of electrons and holes. Over time, these hot carriers break bonds and become trapped, changing electrical properties of the transistor. In NMOS transistors, electron mobility is degraded, causing a reduction in the drive current and hence performance of the transistor.
By industry convention, the lifetime of a transistor is the stress time that elapses until there is a 10% reduction in the drive current due to hot carrier effects. Compensating for the reduction in drive current by increasing the source-to-drain potential difference (V.sub.DS), however, increases local electric fields and rate of hot carrier degradation.
In order to enhance microprocessor speed, we have been investigating the use of sub-minimum (i.e., very deep sub-micron, around 0.25 micron) channel length transistors in stacked NAND gate circuits, commonly part of a microprocessor's critical path. A critical path of a microprocessor is a series of interconnected gates, registers, and other elements through which a propagation delay is determinative of the processing speed of the microprocessor. Therefore, reducing the propagation delay of any element, for example, a NAND gate, in the critical path enables the microprocessor to execute at higher speeds.
Referring to FIG. 1, depicted is a three-input stacked NAND gate 100 implemented in CMOS technology, comprising three PMOS transistors 102, 104, and 106 coupled in parallel and three NMOS transistors 112, 114, and 116 coupled in series. The three-input stacked NAND gate 100 is merely illustrative, because stack NAND gates in a critical path of a microprocessor may comprise up to at least sixteen inputs. In a stacked NAND circuit, the V.sub.DS for each NMOS transistor is typically much less than the supply voltage, especially for the second and third transistors 114 and 116. Since the associated hot carrier effects are smaller due to a smaller electric field, the performance of NMOS transistors 112, 114, and 116 can be improved by reducing their channel lengths as much as possible while maintaining respective device lifetimes within acceptable norms, commonly specified at five or ten years. Since the V.sub.DS for each NMOS transistor 112, 114, and 116 is different from the others, performance and reliability can be improved by using different channel lengths for the transistors. For example, NMOS transistors 112, 114, and 116 may have channel lengths of 0.25 micron, 0.225 micron, and 0.2 micron, respectively. NMOS transistor 112 has the greatest potential difference, V.sub.DS, across it and hence the longest channel length.
In microprocessor design, it is desirable to accurately predict the performance and reliability of the sub-minimum channel transistors in the stacked NAND gates in the critical path of the microprocessor. However, stacked NAND gates and other critical path circuitry are not easily found or readily available as test structures for evaluating hot carrier effects.